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W25Q64DW
10.2.42 Enable Reset (66h) and Reset (99h)
Because of the small package and the limitation on the number of pins, the W25Q64DW provide a
software Reset instruction instead of a dedicated RESET pin. Once the Reset instruction is accepted, any
on-going internal operations will be terminated and the device will return to its default power-on state and
lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch (WEL)
status, Program/Erase Suspend status, Read parameter setting (P7-P0), Continuous Read Mode bit
setting (M7-M0) and Wrap Bit setting (W6-W4).
“Enable Reset (66h)” and “Reset (99h)” instructions can be issued in either SPI mode or QPI mode. To
avoid accidental reset, both instructions must be issued in sequence. Any other commands other than
“Reset (99h)” after the “Enable Reset (66h)” command will disable the “Reset Enable” state. A new
sequence of “Enable Reset (66h)” and “Reset (99h)” is needed to reset the device. Once the Reset
command is accepted by the device, the device will take approximately tRST=30us to reset. During this
period, no command will be accepted.
Data corruption may happen if there is an on-going or suspended internal Erase or Program operation
when Reset command sequence is accepted by the device. It is recommended to check the BUSY bit and
the SUS bit in Status Register before issuing the Reset command sequence.
/CS
Mode 3
0
1
2
3
4
5
6
7
Mode 3
0
1
2
3
4
5
6
7
Mode 3
CLK
Mode 0
Instruction (66h)
Mode 0
Instruction (99h)
Mode 0
DI
(IO 0 )
DO
High Impedance
(IO 1 )
Figure 41a. Enable Reset and Reset Instruction Sequence (SPI Mode)
/CS
Mode 3
0
1
Mode 3
0
1
Mode 3
CLK
Mode 0
I nstructio n
66h
Mode 0
In structio n
99h
Mode 0
IO 0
IO 1
IO 2
IO 3
Figure 41b. Enable Reset and Reset Instruction Sequence (QPI Mode)
Publication Release Date: September 18, 2012
- 67 -
Revision D
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